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ADE7566/ADE7569
ANALOG-TO-DIGITAL CONVERSION
Each ADE7566/ADE7569 has two Σ-Δ analog-to-digital converters
(ADCs). The outputs of these ADCs are mapped directly to
waveform sampling SFRs (Address 0xE2 to Address 0xE7) and
are used for energy measurement internal digital signal processing.
In PSM1 (battery mode) and PSM2 (sleep mode), the ADCs are
powered down to minimize power consumption.
For simplicity, the block diagram in Figure 33 shows a first-
order Σ -Δ ADC. The converter is made up of the Σ -Δ modulator
and the digital low-pass filter.
A Σ - ? modulator converts the input signal into a continuous
serial stream of 1s and 0s at a rate determined by the sampling
clock. In the ADE7566/ADE7569, the sampling clock is equal to
MCLK/5. The 1-bit DAC in the feedback loop is driven by the
serial data stream. The DAC output is subtracted from the input
signal. If the loop gain is high enough, the average value of the
Preliminary Technical Data
40 Hz to 2 kHz. Oversampling has the effect of spreading the
quantization noise (noise due to sampling) over a wider
bandwidth. With the noise spread more thinly over a wider
bandwidth, the quantization noise in the band of interest is
lowered (see Figure 32).
However, oversampling alone is not efficient enough to improve
the signal-to-noise ratio (SNR) in the band of interest. For example,
an oversampling ratio of four is required to increase the SNR by
only 6 dB (1 bit). To keep the oversampling ratio at a reasonable
level, it is possible to shape the quantization noise so that the
majority of the noise lies at the higher frequencies. In the Σ -Δ
modulator, the noise is shaped by the integrator, which has a
high-pass-type response for the quantization noise. The result is
that most of the noise is at the higher frequencies where it can
be removed by the digital low-pass filter. This noise shaping is
shown in Figure 32.
ANTI ALIAS
DAC output (and therefore, the bit stream) can approach that of
DIGITAL
FILTER (RC)
SAMPLING
the input signal level.
SIGNAL
FILTER
SHAPED
FREQUENCY
For any given input value in a single sampling interval, the data
from the 1-bit ADC is virtually meaningless. Only when a large
number of samples are averaged is a meaningful result obtained.
NOISE
NOISE
This averaging is carried into the second part of the ADC, the
digital low-pass filter. By averaging a large number of bits from
0
2
409.6
FREQUENCY (kHz)
819.2
the modulator, the low-pass filter can produce 24-bit data-
words that are proportional to the input signal level.
The Σ -Δ converter uses two techniques to achieve high resolution
from what is essentially a 1-bit conversion technique. The first
SIGNAL
NOISE
HIGH RESOLUTION
OUTPUT FROM DIGITAL
LPF
is oversampling. Oversampling means that the signal is sampled
0
2
409.6
819.2
at a rate (frequency) that is many times higher than the bandwidth
of interest. For example, the sampling rate in the ADE7566/
ADE7569 is MCLK/5 (819.2 kHz), and the band of interest is
MCLK/5
FREQUENCY (kHz)
Figure 32. Noise Reduction Due to Oversampling and
Noise Shaping in the Analog Modulator
ANALOG
LOW-PASS FILTER
R
C
+
–
INTEGRATOR
LATCHED
COMPARATOR
DIGITAL
LOW-PASS
FILTER
24
V REF
... 10100101 ...
1-BIT DAC
Figure 33. First-Order Σ -? ADC
Rev. PrA | Page 42 of 136
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